A traditional dense library layout does not include trench silicide and metal zero (M0) layers. Instead, as illustrated in FIG. 1A, active area contacts (CAs) 101 are used as vertical local interconnects, for example connecting power rails 103 and 105 to active areas 107 and 109, respectively, and the metal 1 (M1) layer includes bidirectional routing (111) for connecting active area 107 to active area 109. In this architecture, a CA 101 is formed between adjacent gate lines 113, metal line 115 and power rails 103 and 105 are part of the M1 layer, a gate contact (CB) 117 connects metal line 115 to an underlying gate line 113, and vias (V0) 119 connect the M1 layer to CAs 101.
Recently, a trench silicide and a metal 0 (M0) layer have been introduced to the traditional architecture to relieve some of the M1 congestion and improve pin accessibility. For example, as illustrated in FIG. 1B, a trench silicide 121 is formed between adjacent gate lines 113, CA 123 connects trench silicide 121 with M0 125 (which is formed below and perpendicular to M1 metal lines 115), and V0 127 connects M0 to metal line 115. Further, metal segments 103 and 105, previously used alone as power-rails, connect through a V0 119 to M0 segments 129, which are used as additional power-rails. As the horizontal routing occurs on the M0 level, which is below M1, congestion at the M1 level is reduced.
However, as illustrated in the top portion of FIG. 1C, at the cell boundary, V0 and M0 must satisfy certain enclosure rules, in which M0 must extend far enough beyond the edge of V0 to ensure proper connection between the two, as the ends of M0 may become rounded during printing. Concurrently, M0 must maintain a reasonable tip-to-tip (T2T) distance 131 for manufacturability, particularly for smaller technology nodes. To satisfy T2T requirements, M0 could be formed wider as shown in the bottom portion of FIG. 1C, such that the distance 133 becomes a side-to-side (S2S) distance. Further, a smaller enclosure can be tolerated when the metal becomes wider. Since printing primarily affects the end or tip of a metal segment, V0 and M0 can tolerate a zero enclosure (in which the edge of M0 aligns with the edge of V0) at the sides if M0 is formed as a vertical line. (Although a zero enclosure is illustrated in FIG. 1C for illustrative purposes, since M0 is not yet a vertical line in this example, in reality a small enclosure would still be required.) However, a wider M0 takes up more space, and, therefore, creates congestion on the M0 level for more complicated cells, and specifically for dense library cells (i.e., cells with 9 tracks and below). In the cases of tall cells, such as with 12 tracks and beyond, this is not a concern, as there are no strict density requirements, and layout engineers can just increase the cell height or slip dummy gate lines at the cell boundary to satisfy any design rules.
A need therefore exists for methodology enabling connections between two active regions and between a metal line and a gate line without violating V0/M0 enclosure rules and with sufficient T2T distance for dense library cells, and the resulting device.